This invention relates generally to means and methods for performing arithmetic operations in a data processor. More particularly, this invention relates to improved means and methods for providing high speed parallel addition and/or subtraction in a digital data processor.
In parallel type digital adders and subtractors, all orders of digits of the two digital operands (which are the addend and augend in the case of addition, or the subtrahend and minuend in the case of subtraction) are applied in parallel to the input, and all digits of the resulting sum or difference are provided in parallel at the output. In such parallel adders or subtractors, provision must, of course, be made for providing the carry or borrow information required for obtaining the correct sum or difference. One approach for providing the required carry and borrow information employes what is known as "propagate" logic in which the carry or borrow information generated in the lowest order position ripples through to the highest order position. However, such propagation takes time and the resulting delays are accumulative, thus a relatively long time may be required for the overall addition or subtraction operation which may be unduly long for many types of applications requiring high speed.
In order to achieve faster operation, a second approach to the design of parallel adders and subtractors has been employed utilizing what is known as "look-ahead" logic which generates the required carry or borrow information in parallel for all orders. Although this look-ahead approach achieves much faster operation than does the propagate approach mentioned above, it has the significant disadvantage of requiring complex logic circuit arrangements which continue to increase in complexity as the number of digits of the operands increases.
A third approach to the design of parallel adders and subtractors utilizes what is known as "conditional" logic in which two conditional results are generated for each order, one assuming the presence of an input carry or borrow, and the other assuming the absence of an input carry or borrow. Selection of the conditional sums is then made based on carry or borrow information derived from lower orders. This conditional approach represents another way of achieving higher speed operation, but also suffers from the disadvantage of requiring increasingly complex logic circuitry as the number of operand digits is increased.